The present invention relates generally to vertical channel electric field controlled semiconductor devices such as field effect transistors and, more particularly, to such devices employing recessed gate structures, and methods for fabricating such devices.
Vertical-channel electric field controlled devices have recently been developed, and are suitable for power switching applications at relatively high voltages, in excess of 500 volts. These devices are of several types, including field effect transistors (FETs) and field controlled thyristors (FCTs), all having similar gate structures. For convenience, the recessed gate structure and fabrication methods of the present invention are described herein primarily with reference to vertical channel FETs. It will be appreciated, however, that the gate structures and fabrication methods are equally applicable to other forms of vertical-channel field semiconductor devices, such as FCTs.
Briefly, in a vertical-channel FET structure, source and drain regions are formed on opposite surfaces of a semiconductor wafer, the source and drain regions both, for example, being of N+ conductivity type. Intermediate the source and drain regions is an N- conductivity type base region, in turn containing a low resistivity P+ grid or gate defining a number of vertical channels. In one particular form of device, the source (or cathode) and gate regions are elongated finger-like structures, with the source (or cathode) and gate regions interdigitated. The devices are normally on, and therefore conduct with zero gate bias. As reverse gate bias is applied, a depletion region is formed which inhibits or blocks conduction vertically through the device.
Such devices are described in the literature, for example, D. E. Houston, S. Krishna, D. E. Piccone, R. J. Finke and Y. S. Sun, "A Field Terminated Diode", IEEE Trans. Electron Devices, Vol. ED-23, No. 8, pp. 905-511. (August 1976). In addition to this Houston et al literature reference, various forms of such devices are disclosed in the commonly-assigned patents to Ferro, U.S. Pat. No. 4,037,245, Houston et al, U.S. Pat. No. 4,060,821, Baliga, U.S. Pat. No. 4,132,996, and Hysell et al, U.S. Pat. No. 4,170,019. Additional disclosures are found in commonly-assigned Baliga and Wessels application Ser. No. 169,853, filed July 17, 1980, entitled "PLANAR GATE TURN OFF FIELD CONTROLLED THYRISTORS AND PLANAR JUNCTION GATE FIELD EFFECT TRANSISTORS, AND METHOD OF MAKING SAME", now abandoned in favor of continuation application Ser. No. 355,005, now abandoned in favor of divisional application Ser. No. 630,473. Application Ser. No. 169,853, is a continuation of now-abandoned application Ser. No. 938,020, filed Aug. 30, 1978, which is in turn a continuation-in-part of now-abandoned application Ser. No. 863,877 filed Dec. 23, 1977.
Heretofore there have been two general structures for these devices: planar or surface gate structures wherein the gate is on the surface of the device; and buried gate structures wherein the gate is buried within the base region. Buried gate devices have the advantage of increased source (or cathode) area compared to surface gate devices because, in surface gate devices, the source (or cathode) region must be located between the gate grids and sufficiently separated therefrom to obtain an acceptably high grid-source (or grid-cathode) breakdown voltage. Buried gate structures overcome this particular problem and enable a higher blocking gain to be achieved. Another advantage of buried grid devices has been the need for less critical photolithographic alignment in fabrication compared to those required for surface gate devices wherein interdigitated gate and source (or cathode) regions are fabricated to close tolerances.
One significant disadvantage to buried gate devices, however, has been that the inability to metallize a buried gate along its entire length results in higher gate resistance, which limits the frequency response of buried grid FETs and FCTs. In typical buried gate devices, remote gate contacts are required, for example, at the periphery of the wafer or device.
A hybrid approach is disclosed in the above-identified commonly-assigned Houston et al U.S. Pat. No. 4,060,821, wherein the gate is divided into surface gate portions and buried gate portions, with the buried gate portions having a greater lateral extent; at the device surface, the surface area of the cathode structure is substantially greater than that of the grid structure. This device, however, is fabricated using diffusion techniques to form the buried gate portion, with the result that the shape of the buried gate is somewhat semi-cylindrical, resulting in an undesirably small channel length-to-width ratio.
In particular, it has recently been appreciated that vertically-walled gate structures wherein the gates or grids are rectangular in cross-section provide significantly higher blocking gain. For example, the above-identified Baliga et al application Ser. No. 630,473 describes planar, junction gate FETs and FCTs having higher forward blocking capabilities and higher blocking gains than diffused-gate devices. As there described, preferential etch and refill techniques may be employed to achieve the substantially vertical walls and rectangular cross-sections. However, the epitaxial refill process is complex, and results in poor yield unless extreme care is taken during the refill to obtain a planar surface with no voids in the grooves.
By the present invention, there is provided a junction gate structure suitable for FETs and FCTs which provides a number of advantages over previous devices. Significantly, the gate fingers are metallized along their entire lengths, providing a low resistance gate connection. Moreover, the structure facilitates a manufacturing process wherein the location of the source (or cathode) and gate regions are defined by a single mask; these regions are thus in effect self-aligned, avoiding the usual photolithographic alignment problems encountered when forming interdigitated source (or cathode) and gate regions. Of additional significance, the need for a critically aligned metal definition step to defining source (or cathode) and gate metallization areas is avoided.